1. Field of the Invention
The present invention relates to a debugging system for use in analyzing operation in various kinds of systems, such as an LSI system which include a microprocessor and, in particular, to a software simulator. Such systems may be, for example, a system which uses a digital synchronizing circuit wherein internal operation can not be directly monitored, a system including an interface which is located between synchronizing circuits and wherein direct monitoring of operation is difficult, or a system using an asynchronous interface such as a serial interface, a high speed bus interface or the like between synchronizing circuits.
2. Description of Related Art
In general, it is a recent trend that not only a single function but also a plurality of functions are incorporated in one chip in a functional LSI represented by a microprocessor with development of the micro fabrication technology. This enables a high speed operation of the system, a multifunction of the system, and a reduction in power consumption of the system and a low cost of the system.
In a system which includes a microprocessor, requirements have been made not only about development of hardware but also about development of a system cooperating with software executed by the microprocessor. Recently, the system tends to become very large and complicated. This renders software and hardware into very large sizes and makes debugging difficult more and more. Further, in order to efficiently carry out the debugging, the operation of the system needs to be observed in details.
Generally, it is possible in a debugging system to observe signals appearing at external terminals of an LSI chip but not to observe signals generated within the LSI chip. Meanwhile, in a microprocessor constituted by an LSI chip of an old type, an operation sequence of an instruction can be observed from outside at every minimum step by writing the instruction from an external memory through an external terminal of the chip.
Herein, it is noted that, with the progress of circuit integration technology, a cache memory tends to be internally included in an LSI chip to execute each instruction. With this structure, most of operation concerned with a writing operation of each instruction is carried out by the use of the cache memory. As a result, it becomes difficult to observe behavior executed in connection with an instruction, by the use of an external terminal of the LSI chip.
Furthermore, a timer, a serial interface, and the like other than the microprocessor is apt to be internally included in the LSI chip. Under the circumstances, this structure make it difficult to analyze behavior of the timer, the serial interface, and the like from an external device and also makes it very difficult to execute debugging operation concerned with these elements.
Taking the above into consideration, a debugging system has been proposed in Japanese Unexamined Patent Publication No. JP-A-5-224989, namely, 224989/1993.
First, description will be made about an outline of a debugging system of a processor which is disclosed in the above publication and which internally includes a cache memory in reference to FIG. 1 (hereinafter, referred to as Conventional Example 1).
A microprocessor 701 which internally includes a cache memory is connected to a main memory 702 through buses. A trace analyzer 703 is connected to the buses to read access of the microprocessor 701 to the main memory 702 and to store it in a trace memory 704.
When the cache memory is kept in an inactive state, reading operations of an instruction of the processor 701 are all carried out of the main memory 702. Accordingly, contents can completely be monitored by the trace analyzer 703. However, when the cache memory is kept in an active state, contents followed by execution of an instruction cannot be monitored by the trace analyzer 703. In this event, a mode display signal 705, an instruction execution start signal 706, a branch instruction occurrence signal 707, and an interruption branch occurrence signal 708 are transmitted from the microprocessor 701 to the trace analyzer 703.
In the active state of the cache memory, the trace analyzer can uniquely estimate an operation of unbranching a program and a static conditional branch operation indicated at a branch destination address, in response to the instruction execution start signal 706 and the branch instruction occurrence signal 707.
Meanwhile, in a branch operation where an address is dynamically determined, estimation of the operation is not feasible only by these terminals. In this case, the trace analyzer 703 should temporarily stop an operation of the microprocessor by sending an interruption to the microprocessor and should confirm the address related to the operation.
However, the stoppage of the operation makes it actually impossible to observe an actual system in real time.
Also, another conventional debugging system has been also disclosed in "Nikkei Electronics, Jul. 31, 1995, pp. 133). Such a conventional debugging system will be described with reference to FIG. 2 and will be referred to as Conventional Example 2. Briefly, the debugging system has a function of supplying branch information to an external device.
Specifically, the illustrated debugging system is formed by a microprocessor 800 and a debugging tool or a trace analyzer 803. In the microprocessor 800 placed on a print board, a debugging circuit 802 which is used only for debugging is connected to a CPU core 801 and is connected to the trace analyzer 803 via a special purpose pin 804 only for debugging. The CPU core 801 supplies output signals to the trace analyzer 803 in synchronism with a sequence of clocks to transmit a state of the CPU core 801 at each clock to the trace analyzer 803. The number of the buses which are used to transmit the signals in the system is equal to four and is comparatively small in comparison with internal states of the microprocessor 800 to be transmitted.
In FIG. 3, illustration is made about a part of contents of signals which are transmitted to the trace analyzer 803 via the special purpose pin 804 for debugging. In each state shown in FIG. 3, a necessary number of instruction execution states is transmitted from the debugging circuit 802 at each clock sent from the CPU core 801. In addition to the illustrated states, a branch destination address is transmitted to the trace analyzer 803 over 30 clocks only when a branch instruction JMP which is undetermined yet appears.
This structure makes it possible to observe a branch to an undetermined address. Thus, a branch to an undetermined address, such as a register indirect jump or the like, which can not be feasible in Conventional Example 1, can be observed without stopping the system. However, such a branch can be observed on one condition that a next following undetermined branch never occurs within the time period of 30 clocks.
Referring to FIG. 4, description will be made about a conventional software simulator which is for use in debugging software (hereinafter, referred to as Conventional Example 3).
A simulation model 401 includes all of models of a system constituted by an instruction executing unit 410, CPU 412 including a cache memory 411, a memory 415, I/O interfaces 1001 and 1002, and a bus 416 connected among them. In this connection, all of the illustrated elements may be considered as the models formed by software programs.
When a program memory initial state 402 is at first loaded into the software simulator, the simulation model 401 is operated at every clock and a result thereof is confirmed by an internal state monitor 404. Thereby, verification is made about normality of a formed system and operation of a program.
The advantage of the software simulator in Conventional Example 3 resides in that all of the operation of the microprocessor and the system can be monitored by a user so far as the models of the external I/O interfaces 1001 and 1002 are completely formed.
Meanwhile, the above-described Conventional Example 2 includes a mechanism for monitoring the operation of a program counter of the microprocessor to observe the execution order or a flow of the instructions. However, it is difficult to find out a cause of a malfunction only by the flow of the instructions, although the flow of the instructions give a clue for grasping the behavior of the system. That is, the malfunction to be corrected is not always caused to occur by the flow of the program per se but is often caused to occur on the basis of input data signals given from the system and a calculation result of the microprocessor. In the latter case, an analysis of the program is further needed for investigating the cause of the operation and correcting the cause.
In addition, an operator should completely understand programs and operation of the systems in the method mentioned in Conventional Example 2. However, inasmuch as an analysis of systems tends to become complexed, extensive, and expanded more and more, improvement of efficiency of debugging cannot probably cope with the enlargement of scale of system because there is a limit about ability of a human. Accordingly, a further support for a debugging environment has been requested.
In order to overcome the above-described drawback, the above-described Conventional Example 3 adopts the method where all of the necessary portions of a system are formed by software models which can observe the internal states. In this event, it is advantageous that not only the execution order of instructions but also all of the operations of the system can be observed with this structure. Moreover, observation can be made with this structure retroactively to a time point before the occurrence of an event to be observed.
However, the Conventional Example 3 has the following significant drawbacks also in comparison with the Conventional Example 2. That is, the software models should be prepared in connection with all hardware units which are present in the system. Furthermore, behavior of the system can not be practically directly reproduced when the malfunction occurs in an actual system. Accordingly, to specify a cause of actual malfunction, it is still indispensable for an operator of a debugging system to estimate the operation of the system and to thereafter identify the cause.
Under the circumstances, it has been found out that the Conventional Example 3 is suitable for aiding or assisting development but is not suitable for analyzing a cause of a malfunction which occurs undesirably in an actual system since the state of the malfunction cannot directly be observed.
At any rate, in analyzing operation of a system which is going to be complicated, both of direct observation of operation actually occurring in the system and detailed observation of an internal state will be simultaneously requested in a future system.
Further, in a large scale system like a recent system, there are the cases where respective synchronizing circuits are operated in synchronism with individual clocks. In this event, it is necessary to monitor input signals on simulating general synchronizing circuits. This brings about necessity of all asynchronous connections of such a device since the input signals need to be monitored on simulating the general synchronizing circuit. The method involves a drawback where all records of communication through asynchronous interfaces are necessary and, as a result, a buffer capacity becomes enormous.
If each interface is operable in synchronism with both of clocks, contents of the interface can be reproduced by using each of the simulation models thereof. However, such simulation models cannot be used in asynchronous transfer of clocks. This is because timings of transfer are varied relative to the clocks each time when execution is carried out. Under this state, all transfer signals should be monitored eventually. This results in necessity of a great amount of of signal hysteresis buffer. Therefore, requirement has been directed to a method of reproducing the contents of transfer only by monitoring a part of signals even in the case of asynchronous transfer.
Further, a high speed interface used in recent years requires electric properties of wirings strictly prescribed. This makes it difficult to connect a probe for observation to the interface from outside. As a result, it becomes difficult to monitor internal operation of a logical circuit and even to monitor all of inputs of signals. In a high speed transfer system, an interface appears which operates each device asynchronously with one another and which carries out synchronous transfer in accordance with synchronizing clocks. With this interface, internal operational timings in such a system cannot be predicted from outside although almost all of the system is constituted by synchronizing circuits. In addition, both systems are operated asynchronously with each other and, therefore, practical transfer timings cannot be accurately determined without actual observation.
Even in such a case having an asynchronous interface, observation of internal operation and coordinating operation are invariably needed. Under the circumstances, a debugging system has been required which is capable of observing internal operations by simulation.